1. Field of the Invention
The present invention generally relates to computer-aided circuit designs. More specifically, the present invention pertains to methods and systems for designing, instrumenting, and debugging integrated circuits.
2. Description of the Related Art
Integrated circuits are designed by designers to operate in specific ways. Once designed, the circuits may need to be analyzed, diagnosed, and debugged. Debugging is a process which involves detection, diagnosis, and correction of functional failures or discrepancies between the intended design and manifested behavior. In the detection phase, the designer of the circuit observes a functional failure. When the designer is able to gather enough information about the behavior of the integrated circuit, the designer of the circuit can draw the necessary conclusions to diagnose the functional failure. To correct the functional failure, a fix is applied and the design is modified. When the design is provided in a Hardware Description Language (HDL), such a fix may be a textual change to the HDL description of the integrated circuit.
During, or subsequent to, the circuit design, instrumentation circuitry may be added to facilitate the analysis, diagnosis and debugging of the integrated circuit design. Various techniques and systems of design instrumentation at an HDL level are described, for example, in the U.S. Pat. No. 6,931,572, which is incorporated herein by reference in its entirety. An electronic monitoring circuit may be provided within an integrated circuit hardware product for assisting a debugger system in debugging the circuit design within the integrated circuit hardware product. A typical electronic monitoring circuit includes a trigger processing unit for monitoring trigger events and issuing a trigger action based on one or more of the monitored trigger events, probe circuits coupled between the integrated circuit hardware product and the trigger processing unit, a configuration register that stores configuration information for use in configuring the trigger processing unit or the probe circuits, and a communication controller operatively connected to the configuration register to provide external access to the configuration register by the debugger system.
After a circuit is designed, certain signals are selected for instrumentation to facilitate the analysis, diagnosis and debugging of the electronic circuit design. Synthesis and place and route are then run on the design with instrumentation circuitry. This is illustrated in a flow diagram shown in FIG. 1, which we call the “initial flow” in this disclosure. At 102, a circuit design is created and compiled. In some cases, the design is created by writing a text representation of a circuit in Hardware Description Language (HDL). The text representation may then be input into a compiler. After compilation, a register transfer level (RTL) netlist may be generated. The RTL netlist usually shows registers and other logic interconnected to show the flow of data through a circuit that was described in the text representation. At 104, one or more signals in the design are selected and instrumented. During instrumentation, a user may select the debugging logic or specify the debugging hardware. Debugging logic is then inserted based on the user's selections. In certain cases, the user may select the number of instrumentation signals and the instrumentation type associated with each signal, such as trigger only, sample only, or trigger and sample. At 106, synthesis and place and route are run on the design. During synthesis, the RTL netlist may be mapped to a target architecture. The mapping operation converts the RTL level representation of the desired circuit into the equivalent circuit implemented using building blocks of the target architecture. A technology specific netlist is generated. Conventional place and route tools may then be used to create a design of circuitry in the target architecture. At 108, the design is debugged. During debugging of the integrated circuit design, the designer may find that one or more signals that should have been instrumented are not or that one or more of the instrumented signals are not necessary. In the prior art methods, the price for adjusting the instrumented signals is high. First, the set of instrumented signals have to be modified. Then, synthesis and place and route have to be rerun on the design. After that, the design may be debugged again. Each time the designer wants to change the set of instrumented signals for a design, this costly process must be repeated.
FIG. 2 illustrates a method for modifying the instrumented signals in the prior art. The initial instrumentation logic is built, for example, according to a method shown in FIG. 1 (“initial flow”), and the circuit design is debugged. When the instrumentation logic needs to be changed, one or more instrumented signals are first modified as illustrated in block 152. Next, synthesis and place & route are rerun on the design, at 154. Then, the design may be debugged again, at 156. Whenever the instrumentation logic needs to be modified, these operations, 152, 154, and 156, are repeated, as indicated by a loop in the flow chart. This prior art method is essentially equivalent to the initial instrumentation process, for example as shown in FIG. 1, in that it requires complete rerunning of synthesis and place & route operations, which can be very time-consuming, among other things.